About me

www.sidjos.com

Contact Email: me@sidjos.com

Technological Institute
Northwestern University
Evanston, Illinois, USA - 60201






I'm a Ph.D. candidate in the Computer Engineering and Systems Laboratory with Prof. Seda Ogrenci-Memik at Northwestern University in Evanston Illinois, USA.

My research till now has focused on associative memory design and testing, and in the fabrication and integration of thin-film thermocouples in 3D ICs for temperature measurement and thermal management. We are working with Dr. Ted Liu and Dr. James Hoff at Fermi National Accelerator Laboratory on a Vertically Integrated Pattern Recognition Associative Memory (VIPRAM) for fast-track finding at the LHC. I have been involved in the complete cycle - from design to testing of a pattern recognition associative memory chip fabricated in 130nm lp CMOS.

I attended B.I.T.S. Pilani in Pilani for my undergraduate. I worked at Intel in Hillsboro, Oregon U.S.A. in Dr. Chandramouli Kashyap's group with Dr. Chirayu Amin in Spring+Summer of 2016; and again in Summer 2018. I have also worked at Fermi National Accelerator Laboratory, Batavia Illinois and C.E.R.N, Geneva Switzerland as a visiting researcher and summer student. I enjoy cricket, squash, video games and classic rock.

Select Publications:
  • "Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization Analysis", S Joshi, D. Li, S Ogrenci-Memik, J Hoff, S Jindariani, T Liu, J Olsen, G. Deptuch, N Tran, JLPEA 2018, Abstract PDF
  • "Performance Study of the First 2D Prototype of Vertically Integrated Pattern Recognition Associative Memory (VIPRAM)", arXiv https://arxiv.org/abs/1709.08303, Gregory Deptuch, James Hoff, Sergo Jindariani, Tiehui Liu, Jamieson Olsen, Nhan Tran, Siddhartha Joshi, Dawei Li, Seda Ogrenci-Memik
  • "Power Characterization and Optimization of 3D CAMs for Tracking Triggers", S. Joshi, S.O. Memik, J. Hoff, T. Liu, (Best Ph.D. Student Presentation Award), International VLSI Design Conference, 2018. https://goo.gl/bLgURx
  • "A Content Addressable Memory with Multi-Vdd Scheme for Low Power Tunable Operation", S Joshi, D. Li, S Ogrenci-Memik, J Hoff, S Jindariani, T Liu, J Olsen, G. Deptuch, N Tran, 60th International IEEE MWSCAS, 2017
  • "End-to-End Analysis of Integration for Thermocouple-Based Sensors Into 3-D ICs", D Li, S Joshi, JH Kim, S Ogrenci-Memik, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017
  • "Thin Film Thermocouple Fabrication Procedure", by S Joshi, G Sundar, F Rao, S Ogrenci-Memik, M Grayson, Northwestern University, 2017
  • "A methodology for power characterization of associative memories", D Li, S Joshi, S Ogrenci-Memik, J Hoff, S Jindariani, T Liu, J Olsen, N Tran, 33rd IEEE International Conference on Computer Design (ICCD), 2015
  • "Design and testing of the first 2D prototype vertically integrated pattern recognition associative memory", T Liu, G Deptuch, J Hoff, S Jindariani, S Joshi, J Olsen, N Tran, M Trimpl, Journal of Instrumentation, 2015
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© Siddhartha Joshi