Update Fall 2019: Graduated with a PhD in Computer Engineering. Joining Intel Corporation, OR USA.
I'm a Ph.D. candidate in Computer Engineering working with Prof. Seda Ogrenci-Memik at Northwestern University in Evanston Illinois, USA. My research is focused on Associative Memory design, verification, and testing; and in the fabrication and integration of thin-film thermocouples in 3D Integrated Circuits for temperature measurement and thermal management. I have previously worked at Intel Corporation OR U.S.A, Fermilab Batavia IL U.S.A., and C.E.R.N. Geneva Switzerland.
Performance Study of the First 2D Prototype of Vertically Integrated Pattern Recognition Associative Memory (VIPRAM), G.W. Deptuch, J.R. Hoff, S. Jindariani, T. Liu, J. Olsen, N. Tran, S. Joshi, D. Li, S. Ogrenci-Memik, IEEE Transactions on Nuclear Science. 2019.
Dynamically Reconfigurable Data Readout of Pixel Detectors for Automatic Synchronization with Data Acquisition Systems. Fahim, F.; Bianconi, S.; Rabinowitz, J.; Joshi, S.; Mohseni, H. Sensors 2020, 20, 2560
High-Speed Readout for Pixel Detectors Based on an Arbitration Tree. Fahim F, Joshi S, Ogrenci-Memik S, Mohseni H. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2019.
The ETROC Project: Precision Timing ASIC Development for LGAD-based CMS Endcap Timing Layer (ETL) Upgrade, Fermilab, Northwestern University, Southern Methodist University, Kyungpook National University (Accepted for presentation) in TWEPP 2019.
Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization Analysis, S. Joshi, D. Li, S. Ogrenci-Memik, J. Hoff, S. Jindariani, T. Liu, J. Olsen, G. Deptuch, N. Tran, JLPEA 2018, Abstract PDF
Workload Dependent Power Estimation of Associative Memory based Tracking Triggers, S. Joshi, S. Ogrenci-Memik, J. Hoff, T. Liu, (IEEE NSS/MIC Trainee Grant Award) IEEE Nuclear Science Symposium 2018
Power Characterization and Optimization of 3D CAMs for Tracking Triggers, S. Joshi, S.O. Memik, J. Hoff, T. Liu, (Best Ph.D. Student Presentation Award), IEEE International VLSI Design Conference, 2018. LINK
A Content Addressable Memory with Multi-Vdd Scheme for Low Power Tunable Operation, S. Joshi, D. Li, S. Ogrenci-Memik, J. Hoff, S. Jindariani, T. Liu, J. Olsen, G. Deptuch, N. Tran, 60th International IEEE MWSCAS, 2017
End-to-End Analysis of Integration for Thermocouple-Based Sensors Into 3-D ICs, D. Li, S. Joshi, J. Kim, S. Ogrenci-Memik, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017 link
VIPRAM L1CMS: a 2-Tier 3D Architecture for Pattern Recognition for Track Finding, J.R. Hoff, G.W. Deptuch, S. Joshi, T. Liu, J. Olsen, A. Shenai, IEEE Nuclear Science Symposium, 2016
A methodology for power characterization of associative memories, D. Li, S. Joshi, S. Ogrenci-Memik, J. Hoff, S. Jindariani, T. Liu, J. Olsen, N. Tran, 33rd IEEE International Conference on Computer Design (ICCD), 2015
Design and testing of the first 2D prototype vertically integrated pattern recognition associative memory, T. Liu, G. Deptuch, J. Hoff, S. Jindariani, S. Joshi, J. Olsen, N. Tran, M. Trimpl, Journal of Instrumentation, 2015
Teaching Experience (TA):
Advanced Digital Logic Design EECS 303
Electronic System Design EECS 395/495
Introduction to Computer Programming II EECS 211
Introduction to Computer Engineering EECS 203